Skip to content

Bitwise Or

The Bitwise Or (denoted as '|') is implemented by applying the following truth table

a b a or b
0 0 0
0 1 1
1 0 1
1 1 1

between each pair of qubits (or qubit and bit) in registers A and B .

Note that integer and fixed-point numbers are represented in a 2-complement method during function evaluation. The binary number is extended in the case of a register size miss-match. For example, the positive signed number \((110)_2=6\) is expressed as \((00110)_2\) when operating with a 5-qubit register. Similarly, the negative signed number \((110)_2=-2\) is expressed as \((11110)_2\).

Examples:

5 | 3 = 7 since 101 | 011 = 111

5 | -3 = -3 since 0101 | 1101 = 1101

-5 | -3 = -1 since 1011 | 1101 = 1111

Syntax

Function: BitwiseOr

Parameters:

{
  "function": "BitwiseOr",
  "function_params": {
    "left_arg": 3,
    "right_arg": {
      "size": 3
    }
  }
}

Register Names

By default, the input registers are called left_arg and right_arg. If the name field of a RegisterUserInput object is specified, then the name of the register is determined accordingly. If one of the arguments is a constant then it is not available as an input register.

The output registers include the result register. By default, it is called bitwise_or, but its name may be overridden by the output_name argument. In addition, since the computation is done out-of-place, input registers are also available as output registers, with the same names.

Example 1: Two Register

{
  "logic_flow": [
    {
      "function": "BitwiseOr",
      "function_params": {
        "left_arg": {
          "size": 5,
          "is_signed": true
        },
        "right_arg": {
          "size": 3
        }
      }
    }
  ]
}
from classiq import ModelDesigner, QUInt, QSInt
from classiq.builtin_functions import BitwiseOr

params = BitwiseOr(
    left_arg=QSInt(size=5).to_register_user_input(),
    right_arg=QUInt(size=3).to_register_user_input(),
)
model_designer = ModelDesigner()
model_designer.BitwiseOr(params)
circuit = model_designer.synthesize()

This example generates a circuit that performs bitwise 'or' between two registers. The left arg is signed with 5 qubits and the right arg is unsigned with 3 qubits.

img_7.png

Example 2: Integer and Register

{
  "logic_flow": [
    {
      "function": "BitwiseOr",
      "function_params": {
        "left_arg": 3,
        "right_arg": {
          "size": 3
        }
      }
    }
  ]
}
from classiq import ModelDesigner
from classiq.builtin_functions import BitwiseOr
from classiq.interface.generator.arith.arithmetic import RegisterUserInput

params = BitwiseOr(left_arg=3, right_arg=RegisterUserInput(size=3))
model_designer = ModelDesigner()
model_designer.BitwiseOr(params)
circuit = model_designer.synthesize()

This example generates a circuit that performs bitwise 'or' between a quantum register and an integer. The left arg is an integer equal to three and the right arg is unsigned quantum register with 3 qubits.

img_8.png